Semiconductor devices, fabrication processes for manufacturing semiconductor devices, and associated test circuits and test structures are well known. On-chip test architectures are often used to check certain characteristics of a semiconductor device (such as a device that implements logic functions using cell libraries) manufactured by a particular process. In this regard, the on-chip test structure is fabricated using the proposed manufacturing process and/or with certain cell libraries to be investigated. Consequently, the on-chip test structure can be exposed to controlled test conditions (e.g., high temperature operating life (HTOL) tests, scan chain tests, radiation tests) to determine how other devices fabricated in accordance with the same process technology might react to the same conditions.
Conventional on-chip test architectures are typically fabricated using symmetric structures that result in symmetric process test patterns. Symmetric patterns tend to repeat only a subset of all possible layout structures. Therefore, when ramping up a manufacturing process using a test design that covers only a subset of all possible layout structures, the process will be optimized to yield only for this subset of layout structures. Afterwards, when manufacturing customer designs that employ the full set of possible layout structures, process yield may unexpectedly go down and production of that customer product may be delayed by an undesirably long time. Accordingly, it is desirable to employ a test design that covers as many layout structures as possible.
Moreover, conventional on-chip test architectures may not be very flexible in nature, i.e., easily able to accommodate different test chip sizes, different process technologies, different cell libraries, and the like. Accordingly, it is desirable to have an efficient and effective semiconductor-based test structure that does not rely on symmetric structures. Moreover, it is desirable to have a configurable on-chip test structure that can be flexibly implemented so as to accommodate a variety of different chip sizes, process technologies, and the like. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.